1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus and a semiconductor device testing method for testing memory and logic sections of a semiconductor device such as a memory-built-in logic LSI with built-in memory and logic sections.
2. Description of the Prior Art
FIG. 6 is a block diagram schematically showing the configuration of a conventional semiconductor device testing apparatus for memory-built-in logic LSIS. In FIG. 6, reference numeral 1 denotes a random pattern memory for storing random patterns composed of input and output patterns of a logic section test signal, 3 an algorithmic pattern generator (hereinafter abbreviated as ALPG) for generating address/data patterns for testing a memory section of an LSI under test, 2 an ALPG instruction memory for storing instructions for the ALPG 3, 4 a pin selector for selecting a pin of the LSI for the application thereto of a test signal, 5 an OR gate, 6 a formatter for determining the timing of rise and fall of a test signal waveform, 9 a random pattern instruction memory for controlling the sequence of execution of random patterns, and 10 an instruction execution part for executing random pattern instructions stored in the instruction memory 9.
The operation of the illustrated semiconductor device testing apparatus will be described below.
For simultaneously testing both of memory and logic sections of a memory-built-in logic LSI under test (hereinafter referred to as a DUT) with a view to increasing test efficiency, the random pattern instruction execution part 10 extracts a random pattern instruction from the instruction memory 9 and follows the instruction to read out a random pattern from the random pattern memory 1. On the other hand, the ALPG3 fetches an ALPG instruction from the instruction memory 2 and follows the instruction to generate an address and data pattern. After the pin selector 4 selects a pin to which the address and data pattern is to be fed, the pattern is logically added by the OR gate 5 to the random pattern from the random pattern memory 1 to form a test signal, which is provided to the formatter 6, wherein the timing of its rise and fall is determined. The test signal is fed to a pin electronics composed of an amplifier, from which it is applied to the pin of the LSI selected by the pin selector 4.
FIG. 7 is a diagrammatic showing of an example of the test pattern that is fed to the semiconductor device testing apparatus of FIG. 6. The test pattern has a configuration that either one or both of instructions for controlling the operation of the ALPG 3 and random pattern instructions are described in a random pattern instruction/ALPG instruction description part. Conventionally, the instructions for the ALPG 3 need to have a one-to-one correspondence with the random test patterns. That is, it is necessary that a one-address ALPG instruction should be prepared for each one-address random test pattern. For this reason, in the case of simultaneously testing logic and memory sections of a memory-built-in logic LSI, since random patterns for logic requires several K to several M addresses, the ALPG instructions, which normally require several to tens of addresses, must be described so that the number of their addresses is equal to that of the random patterns. In concrete terms, the number of addresses of the ALPG instructions is increased, for example, by designating the addresses for the execution of the ALPG instructions by a small amount of addresses.
In the DUT there is a possibility that test results of the logic section, for instance, differ depending on whether the memory section is in its write operation or read operation--this is attributable to noise generation or the like by a difference between the memory operations. To avoid this, the logic section may sometimes be tested using a common random test pattern for every operation of the memory section. In such an instance, it is necessary in the conventional semiconductor device testing apparatus that random patterns for testing the logic section, which are composed of identical two parts for the write and read operations of the memory section, be described together with individual instructions for testing the memory section, as shown in FIG. 8. This inevitably involves the use of a large-scale random pattern memory for storing such an enormous amount of data.
The same goes for the memory section. That is, since test results on the memory section are likely to change with the kind of operation of the logic section, there is a case where the memory section is tested using common data for each operation of the logic section.